1. Field of the Invention
The present invention relates generally to power over Ethernet (PoE) and, more particularly, to a system and method for automatically discovering total transistor resistance in a hybrid PoE architecture.
2. Introduction
In a PoE application such as that described in the IEEE 802.3af and 802.3at specifications, a power sourcing equipment (PSE) delivers power to a powered device (PD) over Ethernet cabling. Various types of PDs exist, including voice over IP (VoIP) phones, wireless LAN access points, Bluetooth access points, network cameras, computing devices, etc.
In accordance with IEEE 802.3af, a PSE can deliver up to 15.4 W of power to a single PD over two wire pairs. In accordance with IEEE 802.at, on the other hand, a PSE may be able to deliver up to 30 W of power to a single PD over two wire pairs. Other proprietary solutions can potentially deliver even higher levels of power to a PD. Those or even higher levels of power can also be provided to a PD over four wire pairs.
PSE subsystems fundamentally rely on some control to “turn on” a power FET, which allows current to be transmitted to the PD. An important factor for the PSE is the resistance of the power FET. This resistance value has an effect on the total heat dissipation and the total allowable current that the PSE can deliver to the PD. In a conventional PSE subsystem design, the resistance of the power FET is a known quantity by design. What is needed, however, is a mechanism that enables a determination of the total FET resistance in PSE designs that include multiple power FETs.